1. Field of the Invention
The subject invention relates generally to large-scale electronic circuit integration technology, and more particularly to an improved power busing scheme for large-scale integrated semiconductor chips.
2. Description of the Prior Art
The tremendous increase in the number of circuit devices such as transistors which can be fabricated on a given semiconductor substrate or "chip" has been a driving force behind the revolutionary advances in and availability of computers and other electronic products. Device density has been increased to the point where the electrical leads or buses used to supply power to the devices occupy an increasingly large share of the chip, reducing the area available for electronic devices.
Present bipolar VLSI chips typically employ an orthogonal bus scheme in which at least 30-40% of the chip area is occupied by the power buses. The power bus size is affected by two factors: (a) the electromigration limit, and (b) the maximum voltage drop tolerated along the bus by the circuit which depends on the technology used to fabricate the devices. With respect to the first factor, as current density increases, aluminum atoms in a conductor are swept into the negative charge stream. This phenomenon may result in deleterious localized heating or open circuits as the concentration of aluminum atoms is locally depleted. With respect to the second factor, the maximum voltage (IR) drop tolerable is that level at which erroneous circuit operation may occur. Erroneous operation may occur because IR drops in buses can slow charging of output capacitances, and can cause improper triggering or activation of devices. Inordinate power consumption and chip heating can result from partial activation of devices which should be in an "off" state.
The busing scheme must also cope with current surges, a particular problem in CMOS designs. The foregoing factors place severe constraints on a bus design, particularly on cross-sectional bus width, which affects current density and electromigration.
Power hungry bipolar technologies such as ECL and integrated injection logic cause aggravation of the above mentioned problems as device density on a single die increases. The higher current densities in more dense circuits cause increased problems with electromigration and IR voltage drop. To alleviate these problems, several things can be done. Among them is the option to decrease current density. One way to do that is to increase the cross sectional area of the bus. However, it is undesirable for the power buses to consume substantial portions of the chip area If more area is consumed by buses, there is less useable chip area upon which to build devices.
There is yet another aspect of the problem not heretofore mentioned. As device size is decreased, the constraints on bus design become more acute. For example, a smaller transistor cannot charge a capacitance as rapidly. Since the leads (e.g., wires) being driven by these smaller VLSI transistors are just as long or longer than those used with physically larger transistors, the parasitic capacitance remains the same, and desired logic levels may take too long to be reached, resulting in erroneous operation or requiring slower clocking rates. Wider buses to handle increased current density have more parasitic capacitance because of greater area of one "plate" of the parasitic capacitor. Therefore wider buses aggravate the problem that was becoming worse by the on-going trend to reduce transistor size.
The response of the prior art to these design limits on device density has been to add additional layers of interconnecting metallization, i.e., third layer and fourth layer metallizations, each separated from the preceding layers by dielectric. Each layer of metallization is of a common thickness. Such schemes entail increased process complexity, requiring two to four additional masks and all the associated steps. Further, each additional mask causes an appreciable reduction in yield. Morever, the full potential of extra layers of metallization cannot be always realized because of the larger vertical connection or "via" required to interconnect the first metallization layer to the third layer through the second and other subsequent layers. The larger vias occupy area which could otherwise be devoted to devices.